Sun Dec 12 15:39:32 2010 efw: Set new output location to 20101212_153932_UUT2_HSK_Module_
Sun Dec 12 15:39:32 2010 FSW_CPT: ========================================
Sun Dec 12 15:39:32 2010 FSW_CPT: *******   HSK MODULE TEST      *********
Sun Dec 12 15:39:32 2010 FSW_CPT: ========================================
Sun Dec 12 15:39:32 2010 efw_cmd_log: EFW_ADRH(221)
Sun Dec 12 15:39:32 2010 efw_cmd_log: EFW_ADRL(255)
Sun Dec 12 15:39:32 2010 efw_cmd_log: EFW_LOAD(0)
Sun Dec 12 15:39:36 2010 efw_cmd_log: EFW_RESET()
Sun Dec 12 15:39:40 2010 efw_error_monitor: SCE_IN_ERRORS.TimePulseTlmUnderrunErrCnt 13
Sun Dec 12 15:39:42 2010 efw_log: 0x0000 1969-12-31 16:00:00 0xc2 0x000001 CMDITFERR ITF Header Error at Address in SRAM
Sun Dec 12 15:39:49 2010 efw_cmd_log: EFW_ADRH(221)
Sun Dec 12 15:39:49 2010 efw_cmd_log: EFW_ADRL(255)
Sun Dec 12 15:39:49 2010 efw_cmd_log: EFW_LOAD(0)
Sun Dec 12 15:39:49 2010 efw_cmd_log: EFW_CLEAR()
Sun Dec 12 15:39:57 2010 FSW_CPT: ========================================
Sun Dec 12 15:39:57 2010 FSW_CPT: *******   FSW VERSION  3.00    *********
Sun Dec 12 15:39:57 2010 FSW_CPT: ========================================
Sun Dec 12 15:39:57 2010 FSW_CPT: ----------------------------------------
Sun Dec 12 15:39:57 2010 FSW_CPT: Starting script TEST_HSK_2.py
Sun Dec 12 15:39:57 2010 FSW_CPT: ========================================
Sun Dec 12 15:39:57 2010 FSW_CPT: HSK_2: ENGINEERING A/D SAMPLING        
Sun Dec 12 15:39:57 2010 FSW_CPT: ========================================
Sun Dec 12 15:39:57 2010 FSW_CPT: 1. Initialization        
Sun Dec 12 15:39:57 2010 efw_cmd_log: EFW_CLEAR()
Sun Dec 12 15:39:57 2010 FSW_CPT: 2.1 Verifying Critical A/D Samples (AP262)
Sun Dec 12 15:39:57 2010 FSW_CPT: TFPGA       [30-50] = 35 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: P33VD       [60-80] = 70 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: P33IMON     [10-20] = 12 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: P15VD       [40-60] = 4c : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: P15IMON     [00-20] = 09 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: 3.1 Verifying General A/D Samples (AP264)
Sun Dec 12 15:39:57 2010 FSW_CPT: IMON_IDPU    [1a-3a] = 31 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: IMON_BEB    [32-52] = 42 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: TMON_LVPS    [6f-8f] = 7f : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: IMON_FVX    [70-90] = 80 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: IMON_FVY    [e0-ff] = ff : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: IMON_FVZ    [1c-3c] = 31 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_BEB_P10VA    [5c-7c] = 6c : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_BEB_N10VA    [83-a3] = 93 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_BEB_P5VA    [56-76] = 66 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_BEB_P5VD    [4c-6c] = 5c : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_IDPU_P10VA    [59-79] = 69 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_IDPU_N10VA    [86-a6] = 96 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_IDPU_P5VA    [53-73] = 63 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_IDPU_N5VA    [8c-ac] = 9c : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_IDPU_P5VD    [55-75] = 64 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_IDPU_P36VD    [54-74] = 6e : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: VMON_IDPU_P18VD    [6b-8b] = 7f : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: TMON_AXB5    [e0-ff] = ff : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: TMON_AXB6    [e0-ff] = ff : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: TEMP_FPGA    [30-50] = 35 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: P33VD        [60-80] = 70 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: P33IMON      [10-20] = 12 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: P15VD        [40-60] = 4c : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: P15IMON      [00-20] = 09 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: DGND         [00-20] = 00 : PASS
Sun Dec 12 15:39:57 2010 FSW_CPT: HSK_2: A/D SAMPLING TEST : 0 Errors
Sun Dec 12 15:39:57 2010 FSW_CPT: ================END====================
Sun Dec 12 15:39:57 2010 FSW_CPT: Script TEST_HSK_2.py completed
Sun Dec 12 15:39:57 2010 FSW_CPT: ----------------------------------------
Sun Dec 12 15:39:57 2010 FSW_CPT: Starting script TEST_HSK_3.py
Sun Dec 12 15:39:57 2010 FSW_CPT: ========================================
Sun Dec 12 15:39:57 2010 FSW_CPT: HSK_3: Limit BEB sampling to LDAC cmd   
Sun Dec 12 15:39:57 2010 FSW_CPT: ========================================
Sun Dec 12 15:39:57 2010 FSW_CPT: 1. Initialization        
Sun Dec 12 15:39:57 2010 efw_cmd_log: EFW_CLEAR()
Sun Dec 12 15:39:58 2010 FSW_CPT: 2.1 Verifying that BEB packet rate == 0
Sun Dec 12 15:40:08 2010 FSW_CPT: 2.1 Verified
Sun Dec 12 15:40:08 2010 FSW_CPT: 2.2 Requesting a Readback from BEB
Sun Dec 12 15:40:08 2010 efw_cmd_log: EFW_LDAC(1)
Sun Dec 12 15:40:14 2010 FSW_CPT: 2.2 Received a Readback : PASS
Sun Dec 12 15:40:14 2010 FSW_CPT: ================END====================
Sun Dec 12 15:40:14 2010 FSW_CPT: Script TEST_HSK_3.py completed
Sun Dec 12 15:40:14 2010 FSW_CPT: ========================================
Sun Dec 12 15:40:14 2010 FSW_CPT: **** HSK Module PASS ****
Sun Dec 12 15:40:14 2010 FSW_CPT: ========================================
Sun Dec 12 15:40:14 2010 FSW_CPT: Script TEST_HSK.py completed
Sun Dec 12 15:40:14 2010 FSW_CPT: ----------------------------------------
Sun Dec 12 15:40:14 2010 FSW_CPT: Starting script TEST_LD.py
Sun Dec 12 15:40:14 2010 efw: Chaging test name to: LD_Module_
Sun Dec 12 15:40:14 2010 efw: Flushing PTP data to disk
Sun Dec 12 15:40:14 2010 efw: Syncing data with rsync (if enabled)