Sat Dec 11 17:59:28 2010 efw: Set new output location to 20101211_175928_UUT2_HSK_Module_ Sat Dec 11 17:59:28 2010 FSW_CPT: ======================================== Sat Dec 11 17:59:28 2010 FSW_CPT: ******* HSK MODULE TEST ********* Sat Dec 11 17:59:28 2010 FSW_CPT: ======================================== Sat Dec 11 17:59:28 2010 efw_cmd_log: EFW_ADRH(221) Sat Dec 11 17:59:28 2010 efw_cmd_log: EFW_ADRL(255) Sat Dec 11 17:59:28 2010 efw_cmd_log: EFW_LOAD(0) Sat Dec 11 17:59:31 2010 efw_cmd_log: EFW_RESET() Sat Dec 11 17:59:36 2010 efw_error_monitor: SCE_IN_ERRORS.TimePulseTlmUnderrunErrCnt 11 Sat Dec 11 17:59:37 2010 efw_log: 0x0000 1969-12-31 16:00:00 0xc2 0x000001 CMDITFERR ITF Header Error at Address in SRAM Sat Dec 11 17:59:44 2010 efw_cmd_log: EFW_ADRH(221) Sat Dec 11 17:59:44 2010 efw_cmd_log: EFW_ADRL(255) Sat Dec 11 17:59:44 2010 efw_cmd_log: EFW_LOAD(0) Sat Dec 11 17:59:44 2010 efw_cmd_log: EFW_CLEAR() Sat Dec 11 17:59:52 2010 FSW_CPT: ======================================== Sat Dec 11 17:59:52 2010 FSW_CPT: ******* FSW VERSION 3.00 ********* Sat Dec 11 17:59:52 2010 FSW_CPT: ======================================== Sat Dec 11 17:59:52 2010 FSW_CPT: ---------------------------------------- Sat Dec 11 17:59:52 2010 FSW_CPT: Starting script TEST_HSK_2.py Sat Dec 11 17:59:52 2010 FSW_CPT: ======================================== Sat Dec 11 17:59:52 2010 FSW_CPT: HSK_2: ENGINEERING A/D SAMPLING Sat Dec 11 17:59:52 2010 FSW_CPT: ======================================== Sat Dec 11 17:59:52 2010 FSW_CPT: 1. Initialization Sat Dec 11 17:59:52 2010 efw_cmd_log: EFW_CLEAR() Sat Dec 11 17:59:52 2010 FSW_CPT: 2.1 Verifying Critical A/D Samples (AP262) Sat Dec 11 17:59:52 2010 FSW_CPT: TFPGA [30-50] = 35 : PASS Sat Dec 11 17:59:52 2010 FSW_CPT: P33VD [60-80] = 70 : PASS Sat Dec 11 17:59:52 2010 FSW_CPT: P33IMON [10-20] = 12 : PASS Sat Dec 11 17:59:52 2010 FSW_CPT: P15VD [40-60] = 4c : PASS Sat Dec 11 17:59:52 2010 FSW_CPT: P15IMON [00-20] = 09 : PASS Sat Dec 11 17:59:52 2010 FSW_CPT: 3.1 Verifying General A/D Samples (AP264) Sat Dec 11 17:59:52 2010 FSW_CPT: IMON_IDPU [1a-3a] = 31 : PASS Sat Dec 11 17:59:52 2010 FSW_CPT: IMON_BEB [32-52] = 41 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: TMON_LVPS [6f-8f] = 7f : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: IMON_FVX [70-90] = 80 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: IMON_FVY [e0-ff] = ff : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: IMON_FVZ [1c-3c] = 29 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_BEB_P10VA [5c-7c] = 6c : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_BEB_N10VA [83-a3] = 93 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_BEB_P5VA [56-76] = 66 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_BEB_P5VD [4c-6c] = 5c : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_IDPU_P10VA [59-79] = 69 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_IDPU_N10VA [86-a6] = 96 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_IDPU_P5VA [53-73] = 63 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_IDPU_N5VA [8c-ac] = 9c : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_IDPU_P5VD [55-75] = 64 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_IDPU_P36VD [54-74] = 6e : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: VMON_IDPU_P18VD [6b-8b] = 7f : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: TMON_AXB5 [e0-ff] = ff : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: TMON_AXB6 [e0-ff] = ff : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: TEMP_FPGA [30-50] = 35 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: P33VD [60-80] = 70 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: P33IMON [10-20] = 12 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: P15VD [40-60] = 4c : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: P15IMON [00-20] = 09 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: DGND [00-20] = 00 : PASS Sat Dec 11 17:59:53 2010 FSW_CPT: HSK_2: A/D SAMPLING TEST : 0 Errors Sat Dec 11 17:59:53 2010 FSW_CPT: ================END==================== Sat Dec 11 17:59:53 2010 FSW_CPT: Script TEST_HSK_2.py completed Sat Dec 11 17:59:53 2010 FSW_CPT: ---------------------------------------- Sat Dec 11 17:59:53 2010 FSW_CPT: Starting script TEST_HSK_3.py Sat Dec 11 17:59:53 2010 FSW_CPT: ======================================== Sat Dec 11 17:59:53 2010 FSW_CPT: HSK_3: Limit BEB sampling to LDAC cmd Sat Dec 11 17:59:53 2010 FSW_CPT: ======================================== Sat Dec 11 17:59:53 2010 FSW_CPT: 1. Initialization Sat Dec 11 17:59:53 2010 efw_cmd_log: EFW_CLEAR() Sat Dec 11 17:59:53 2010 FSW_CPT: 2.1 Verifying that BEB packet rate == 0 Sat Dec 11 18:00:03 2010 FSW_CPT: 2.1 Verified Sat Dec 11 18:00:03 2010 FSW_CPT: 2.2 Requesting a Readback from BEB Sat Dec 11 18:00:03 2010 efw_cmd_log: EFW_LDAC(1) Sat Dec 11 18:00:09 2010 FSW_CPT: 2.2 Received a Readback : PASS Sat Dec 11 18:00:09 2010 FSW_CPT: ================END==================== Sat Dec 11 18:00:09 2010 FSW_CPT: Script TEST_HSK_3.py completed Sat Dec 11 18:00:09 2010 FSW_CPT: ======================================== Sat Dec 11 18:00:09 2010 FSW_CPT: **** HSK Module PASS **** Sat Dec 11 18:00:09 2010 FSW_CPT: ======================================== Sat Dec 11 18:00:09 2010 FSW_CPT: Script TEST_HSK.py completed Sat Dec 11 18:00:09 2010 FSW_CPT: ---------------------------------------- Sat Dec 11 18:00:09 2010 FSW_CPT: Starting script TEST_LD.py Sat Dec 11 18:00:09 2010 efw: Chaging test name to: LD_Module_ Sat Dec 11 18:00:09 2010 efw: Flushing PTP data to disk Sat Dec 11 18:00:09 2010 efw: Syncing data with rsync (if enabled)